The Through Silicon Vias (TSVs) in a 3D stack are the channels for transferring signals between different tiers in a 3D stack. The functionality of a 3D integrated circuit strongly depends on the fidelity of signals through TSVs. Defects can be created in the TSV process while forming the TSVs before bonding (assuming a via-first process) or while bonding different dies together. Specifically, TSVs are susceptible to short defects. A short during TSV formation creates a resistive defect through the oxide. Since the substrate surrounding the TSVs is strongly connected to ground, this results in a low resistive path between the TSV and ground. Such shorts in the TSV will result in partial or complete degradation of signal quality. When the TSV is driven by a driver, the signal swing and/or slew at the receiver end can vary significantly resulting in either complete or partial signal degradation. Therefore, maintaining the signal fidelity through TSVs, especially on critical interfaces such as high speed serial links which establish communication in a system on a chip, is a primary challenge in 3D system integration. TSV technology drives the integration of chips in 3D packaging and overall integrated circuit reliability depends on TSVs and therefore it is important for TSVs to be free from defects.